1. Field of the Invention
The present invention relates to programmable logic arrays (PLAs). More specifically, the present invention relates to macrocells for programmable array logic circuits (PALs).
While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the present invention would be of significant utility.
2. Description of the Related Art
Programmable logic arrays provide `glue logic` for PC (printed circuit) boards. Glue logic is the logic required to interface two boards and generally includes a plurality of AND gates, OR gates and input/output I/O buffers. PLAs consume less space and therefore generally provide glue logic in a less costly manner than individual AND gates, OR gates and I/O buffers.
PLAs also offer the advantage of reconfigurability over discrete or individual gates. That is, PLAs generally include an array of `AND` gates, an array of `OR` gates, and some provision for interconnecting the outputs of selected AND gates to the inputs of selected OR gates. PLAs allow a wide variety of logic functions to be implemented through the combination, via the OR gates, of the product terms, provided by the AND gates. Further, the configuration of the array may be quickly, easily and relatively inexpensively reprogrammed to implement other functions.
As described in U.S. Pat. No. 4,124,899, programmable array logic circuits were developed to provide further improvements in the speed, space requirements, cost and power consumption of PLAs. In a most general sense, a PAL provides a field programmable logic array in which a programmable array of circuit inputs are provided to a plurality of AND gates to generate product terms. Outputs from subgroups of AND gates are, in turn, nonprogrammably connected as inputs to individual, specified OR gates to provide the sum of products. Hence, PALs provide programmable AND and fixed OR functions relative to generic PLAs.
More specifically, a typical PAL includes a plurality of input and output pads which are essentially connection areas and which facilitate the bonding of a first circuit to another circuit via the `glue logic` provided by the PAL. Each input pad is connected to an input buffer which includes circuitry for detecting address transitions at a corresponding input pad. Each input buffer is connected to the logic array. The logic array provides programmable AND and fixed OR product terms to a set of sense amplifiers. The sense amplifiers detect state changes in the array and provide the array outputs to a plurality of latch blocks. The latch blocks are each connected to a macrocell. The macrocells provide register functions (enable control, D flip-flop, set and reset control and etc.), other output functions, information and state control to an associated output pad.
There is an ongoing effort in the art to reduce the parts count, simplify the design and the reduce the power consumption of PALs.